Digital Design

VLSI CMOS Digital Design

Credits: 5.

Period: September-December.

Course Manager: Thomas Olsson, email: Thomas.Olsson@es.lth.se, homepage: http://www.es.lth.se/home/ton/



The course will be given as four two-day meetings at LTH. The first two-day meeting is in 2004-09-20 to 2004-09-21.



Sign up: Before September 1 by email to: secretary@pcc.lth.se

Examination: Laboratory sessions, hand-in exercises and a small project assignment.

Goals and Contents

Preliminary Schedule: ( Please contact Thomas Olsson (Thomas.Olsson@es.lth.se) if any of the dates are not suitable. )
Time / Meeting nr 1. September 20-21 2. October 18-19 3. November 1-2 4. November 15-16
Day 1 1015-1200 Introduction / CMOS transistor Sequential components VHDL Power/Energy consumption
Day 1 1315-1500 Logic gates (1) Arithmetics / Bit serial FPGA / Memory Signal integrity/Chip Economics
Day 1 1515-1700 Logic gates (2) Arithmetics / VHDL Clocking in system design Asynchronous design
Day 2 815-1200 Lab 1. The inverter Lab 2. Standard cells Lab 3. VHDL simulation/synthesis Lab 4. Place & Route
Day 2 1315-1500 Lab preparation / Seminar Lab preparation / Seminar Lab preparation / Seminar Seminar





The course meetings will be in room E:2349, located near the coffee room at the deparment of Electroscience in builing E at LTH. See map to find building E.



Literature: Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nicolic: Digital Integrated Circuits: A Design Perspective, Prentice Hall International Editions, ISBN 0-13-120764-4. http://bwrc.eecs.berkeley.edu/icbook/.





Labs:

lab1

lab2

Cadence shortcuts

lab3

Remote login

a VHDL simulator

The median filter VHDL-files (.zip)

lab4

The ALU VHDL-files (.zip)







Handouts:

Session 1 (14 MB)

Session 2 (6.5 MB)

Session 3 (9.2 MB)